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CODES
2006
IEEE
15 years 3 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
ARC
2008
Springer
141views Hardware» more  ARC 2008»
15 years 1 months ago
A Parallel Hardware Architecture for Image Feature Detection
Abstract. This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architect...
Vanderlei Bonato, Eduardo Marques, George A. Const...
JIRS
2007
108views more  JIRS 2007»
14 years 11 months ago
Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs
This paper presents a methodology for the realization of intelligent, task-based reconfiguration of the computational hardware for mobile robot applications. Task requirements are ...
Sesh Commuri, V. Tadigotla, L. Sliger
DATE
2005
IEEE
162views Hardware» more  DATE 2005»
15 years 5 months ago
A Model-Based Approach for Executable Specifications on Reconfigurable Hardware
UML 2.0 provides a rich set of diagrams for systems documentation and specification. Many efforts have been undertaken to employ different aspects of UML for multiple domains, mai...
Tim Schattkowsky, Wolfgang Müller 0003, Achim...
FPT
2005
IEEE
142views Hardware» more  FPT 2005»
15 years 5 months ago
Custom Hardware Architectures for Posture Analysis
This paper describes the design and implementation of hardware architectures for posture analysis. Posture analysis is an active research area in computer vision. It can be used i...
M. P. T. Juvonen, José Gabriel F. Coutinho,...