211 search results - page 11 / 43 » REDEFIS: a system with a redefinable instruction set process... |
122
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VLSID
1999
IEEE
15 years 1 months ago
1999
IEEE
In hardware - software codesign paradigm often a performance estimation of the system is needed for hardware - software partitioning. The tremendous growth of application specific...
102
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FMCAD
1998
Springer
15 years 1 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
74
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ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
78
Voted
VLSID
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a p...
87
Voted
DSN
2004
IEEE
15 years 1 months ago
2004
IEEE
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...