29 search results - page 2 / 6 » RESIST: a recursive test pattern generation algorithm for pa... |
ISCAS
2007
IEEE
14 years 17 days ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
MEMOCODE
2007
IEEE
14 years 16 days ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
VTS
2008
IEEE
14 years 19 days ago
2008
IEEE
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
ET
2010
13 years 4 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
ICCAD
1997
IEEE
13 years 10 months ago
1997
IEEE
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...