Sciweavers

29 search results - page 6 / 6
» RESIST: a recursive test pattern generation algorithm for pa...
Sort
View
ITC
2003
IEEE
134views Hardware» more  ITC 2003»
13 years 11 months ago
Effectiveness Improvement of ECR Tests
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
Wanli Jiang, Erik Peterson, Bob Robotka
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
13 years 10 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
13 years 11 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri
JSS
2008
122views more  JSS 2008»
13 years 4 months ago
Traffic-aware stress testing of distributed real-time systems based on UML models using genetic algorithms
This report presents a model-driven, stress test methodology aimed at increasing chances of discovering faults related to network traffic in Distributed Real-Time Systems (DRTS). T...
Vahid Garousi, Lionel C. Briand, Yvan Labiche