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» RTL-Datapath Verification using Integer Linear Programming
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132
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CAV
2008
Springer
139views Hardware» more  CAV 2008»
15 years 2 months ago
CSIsat: Interpolation for LA+EUF
We present CSIsat, an interpolating decision procedure for the quantifier-free theory of rational linear arithmetic and equality with uninterpreted function symbols. Our implementa...
Dirk Beyer, Damien Zufferey, Rupak Majumdar
94
Voted
AI
2011
Springer
14 years 7 months ago
Expressive markets for donating to charities
When donating money to a (say, charitable) cause, it is possible to use the contemplated donation as a bargaining chip to induce other parties interested in the charity to donate ...
Vincent Conitzer, Tuomas Sandholm
109
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ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
15 years 9 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
118
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LCTRTS
2009
Springer
15 years 7 months ago
Synergistic execution of stream programs on multicores with accelerators
The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. The StreamIt graphs describe task, da...
Abhishek Udupa, R. Govindarajan, Matthew J. Thazhu...
DAC
2003
ACM
16 years 1 months ago
Accurate timing analysis by modeling caches, speculation and their interaction
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
Xianfeng Li, Tulika Mitra, Abhik Roychoudhury