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» RTOS Modeling for System Level Design
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ASPDAC
2012
ACM
288views Hardware» more  ASPDAC 2012»
13 years 5 months ago
Automatic timing granularity adjustment for host-compiled software simulation
—Host-compiled simulation has been widely adopted as a practical approach for fast and high-level evaluation of complex software-intensive systems at early stages of the design p...
Parisa Razaghi, Andreas Gerstlauer
DATE
2009
IEEE
105views Hardware» more  DATE 2009»
15 years 4 months ago
UMTS MPSoC design evaluation using a system level design framework
Rapid design space exploration with accurate models is necessary to improve designer productivity at the electronic system level. We describe how to use a new event-based design f...
Douglas Densmore, Alena Simalatsar, Abhijit Davare...
DAC
2004
ACM
15 years 10 months ago
System design for DSP applications in transaction level modeling paradigm
In this paper, we systematically define three transaction level TLMs), which reside at different levels of abstraction between the functional and the implementation model of a DSP...
Abhijit K. Deb, Axel Jantsch, Johnny Öberg
DSD
2006
IEEE
110views Hardware» more  DSD 2006»
15 years 3 months ago
A Flexible, Syntax Independent Representation (SIR) for System Level Design Models
System Level Design (SLD) is widely seen as a solution for bridging the gap between chip complexity and design productivity of Systems on Chip (SoC). SLD relieves the designer fro...
Ines Viskic, Rainer Dömer
EURODAC
1995
IEEE
152views VHDL» more  EURODAC 1995»
15 years 1 months ago
Information model of a compound graph representation for system and architecture level design
In order to extract a suitable common core information model, design representations on both system and architecture levels are analyzed. Following the specification trajectory, ...
Peter Conradi