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» RTOS Modeling for System Level Design
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DATE
2005
IEEE
154views Hardware» more  DATE 2005»
15 years 3 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
AHS
2007
IEEE
251views Hardware» more  AHS 2007»
15 years 1 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan
VLSISP
2008
134views more  VLSISP 2008»
14 years 9 months ago
Calibration of Abstract Performance Models for System-Level Design Space Exploration
ion of Abstract Performance Models for System-Level Design Space Exploration ANDY D. PIMENTEL, MARK THOMPSON, SIMON POLSTRA AND CAGKAN ERBAS Computer Systems Architecture Group, In...
Andy D. Pimentel, Mark Thompson, Simon Polstra, Ca...
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CODES
2009
IEEE
15 years 1 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
TC
1998
14 years 9 months ago
Using System-Level Models to Evaluate I/O Subsystem Designs
—We describe a system-level simulation model and show that it enables accurate predictions of both I/O subsystem and overall system performance. In contrast, the conventional app...
Gregory R. Ganger, Yale N. Patt