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» Radiosity on Graphics Hardware
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90
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DAC
2009
ACM
16 years 1 months ago
Event-driven gate-level simulation with GP-GPUs
Logic simulation is a critical component of the design tool flow in modern hardware development efforts. It is used widely ? from high-level descriptions down to gate-level ones ?...
Debapriya Chatterjee, Andrew DeOrio, Valeria Berta...
ICCD
2000
IEEE
125views Hardware» more  ICCD 2000»
15 years 9 months ago
Architectural Support for Dynamic Memory Management
Recent advances in software engineering, such as graphical user intevaces and object-oriented programming, have caused applications to become more memory intensive. These applicat...
J. Morris Chang, Witawas Srisa-an, Chia-Tien Dan L...
ISCAS
2006
IEEE
142views Hardware» more  ISCAS 2006»
15 years 6 months ago
An efficient texture cache for programmable vertex shaders
Vertex texturing is state-of-the-art functionality of vertex. Thus, traditional texture caches used in RE are not the 3D geometry processor. However, it aggravates the always appli...
Seunghyun Cho, Chang-Hyo Yu, Lee-Sup Kim
76
Voted
DAC
2000
ACM
15 years 5 months ago
Using general-purpose programming languages for FPGA design
ct General-purpose programming languages (GPL) are effective vehicles for FPGA design because they are easy to use, extensible, widely available, and can be used to describe both t...
Brad L. Hutchings, Brent E. Nelson
ARC
2010
Springer
183views Hardware» more  ARC 2010»
15 years 1 months ago
Integrated Design Environment for Reconfigurable HPC
Using FPGAs to accelerate High Performance Computing (HPC) applications is attractive, but has a huge associated cost: the time spent, not for developing efficient FPGA code but fo...
Lilian Janin, Shoujie Li, Doug Edwards