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TCAD
1998
82views more  TCAD 1998»
15 years 5 months ago
LOT: Logic Optimization with Testability. New transformations for logic synthesis
—A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K...
166
Voted
ICCAD
2009
IEEE
119views Hardware» more  ICCAD 2009»
15 years 4 months ago
Iterative layering: Optimizing arithmetic circuits by structuring the information flow
Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs ...
Ajay K. Verma, Philip Brisk, Paolo Ienne
INFOCOM
2007
IEEE
16 years 17 days ago
Optimal Policies for Distributed Data Aggregation in Wireless Sensor Networks
Abstract— We consider the scenario of distributed data aggregation in wireless sensor networks, where each sensor can obtain and estimate the information of the whole sensing fi...
Zhenzhen Ye, Alhussein A. Abouzeid, Jing Ai
CORR
2011
Springer
200views Education» more  CORR 2011»
15 years 1 months ago
An Analysis of Optimal Link Bombs
We analyze the recent phenomenon termed a Link Bomb, and investigate the optimal attack pattern for a group of web pages attempting to link bomb a specific web page. The typical ...
Sibel Adali, Tina Liu, Malik Magdon-Ismail
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
16 years 3 months ago
Test-access mechanism optimization for core-based three-dimensional SOCs
— Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Su...
Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yua...