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MICRO
2006
IEEE
159views Hardware» more  MICRO 2006»
13 years 6 months ago
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
13 years 10 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik
LCN
2005
IEEE
13 years 12 months ago
Probabilistic Coverage in Wireless Sensor Networks
— The sensing capabilities of networked sensors are affected by environmental factors in real deployment and it is imperative to have practical considerations at the design stage...
Nadeem Ahmed, Salil S. Kanhere, Sanjay Jha
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 3 months ago
A Probabilistic-Based Design Methodology for Nanoscale Computation
As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research p...
R. Iris Bahar, Joseph L. Mundy, Jie Chen
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
13 years 10 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey