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ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 9 months ago
A non-uniform cache architecture for low power system design
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
Tohru Ishihara, Farzan Fallah
ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 9 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
16 years 29 days ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
GLVLSI
2009
IEEE
170views VLSI» more  GLVLSI 2009»
15 years 8 months ago
Physical unclonable function and true random number generator: a compact and scalable implementation
Physical Unclonable Functions (PUF) and True Random Number Generators (TRNG) are two very useful components in secure system design. PUFs can be used to extract chip-unique signat...
Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, P...
RTS
2010
121views more  RTS 2010»
15 years 2 months ago
A compiler framework for the reduction of worst-case execution times
The current practice to design software for real-time systems is tedious. There is almost no tool support that assists the designer in automatically deriving safe bounds of the wor...
Heiko Falk, Paul Lokuciejewski