1518 search results - page 180 / 304 » Rapid Embedded Hardware Software System Generation |
128
click to vote
SAMOS
2009
Springer
15 years 10 months ago
2009
Springer
We believe that future many-core architectures should support a simple and scalable way to execute many threads that are generated by parallel programs. A good candidate to impleme...
138
click to vote
APCSAC
2001
IEEE
15 years 7 months ago
2001
IEEE
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
154
click to vote
CODES
2006
IEEE
15 years 10 months ago
2006
IEEE
Modern embedded systems for image processing involve increasingly complex levels of functionality under real-time and resourcerelated constraints. As this complexity increases, th...
139
click to vote
VLSISP
2008
15 years 4 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
165
click to vote
CODES
2009
IEEE
15 years 8 months ago
2009
IEEE
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...