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ICCAD
2009
IEEE
118views Hardware» more  ICCAD 2009»
15 years 1 months ago
Memory organization and data layout for instruction set extensions with architecturally visible storage
Present application specific embedded systems tend to choose instruction set extensions (ISEs) based on limitations imposed by the available data bandwidth to custom functional un...
Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leb...
136
Voted
APCCAS
2002
IEEE
156views Hardware» more  APCCAS 2002»
15 years 8 months ago
Bit-plane watermarking for zerotree-coded images
In this paper, we develop a robust bit-plane watermarking technique based on zerotree coding. A robust watermark is an imperceptible but indelible code that can be used for owners...
Shih-Hsuan Yang, Hsin-Chang Chen
CASES
2008
ACM
15 years 5 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...
150
Voted
FECS
2010
236views Education» more  FECS 2010»
15 years 1 months ago
Development of a system for teaching CS1 in C/C++ with Lego NXT robots
This paper describes the development of a system for teaching C/C++ using a LegoTM NXT in a CSI college course on introductory programming. The programming of the NXT robot has be...
Amy Delman, Adiba Ishak, Lawrence Goetz, Mikhail K...
129
Voted
CASES
2007
ACM
15 years 7 months ago
An integrated ARM and multi-core DSP simulator
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
Sharad Singhai, MingYung Ko, Sanjay Jinturkar, May...