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MEMOCODE
2008
IEEE
15 years 9 months ago
Virtual prototyping AADL architectures in a polychronous model of computation
While synchrony and asynchrony are two distinct concepts of concurrency theory, effective and formally defined embedded system design methodologies usually mix the best from both...
Ma Yue, Jean-Pierre Talpin, Thierry Gautier
DAC
2009
ACM
15 years 7 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen
PLDI
2003
ACM
15 years 8 months ago
A comparison of empirical and model-driven optimization
Empirical program optimizers estimate the values of key optimization parameters by generating different program versions and running them on the actual hardware to determine which...
Kamen Yotov, Xiaoming Li, Gang Ren, Michael Cibuls...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 1 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
FPL
2009
Springer
107views Hardware» more  FPL 2009»
15 years 8 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...