Sciweavers

166 search results - page 30 / 34
» Rapid prototyping for kinetic architecture
Sort
View
FCCM
2007
IEEE
122views VLSI» more  FCCM 2007»
15 years 3 months ago
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing
While medium- and large-sized computing centers have increasingly relied on clusters of commodity PC hardware to provide cost-effective capacity and capability, it is not clear th...
Ron Sass, William V. Kritikos, Andrew G. Schmidt, ...
IPPS
2000
IEEE
15 years 3 months ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather
ISPASS
2009
IEEE
15 years 6 months ago
Evaluating GPUs for network packet signature matching
Modern network devices employ deep packet inspection to enable sophisticated services such as intrusion detection, traffic shaping, and load balancing. At the heart of such servi...
Randy Smith, Neelam Goyal, Justin Ormont, Karthike...
FPL
2009
Springer
107views Hardware» more  FPL 2009»
15 years 3 months ago
An FPGA based verification platform for HyperTransport 3.x
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...
Heiner Litz, Holger Fröning, Maximilian Th&uu...
PASTE
2010
ACM
15 years 2 months ago
The RoadRunner dynamic analysis framework for concurrent programs
ROADRUNNER is a dynamic analysis framework designed to facilitate rapid prototyping and experimentation with dynamic analyses for concurrent Java programs. It provides a clean API...
Cormac Flanagan, Stephen N. Freund