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83
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MICRO
2005
IEEE
114views Hardware» more  MICRO 2005»
15 years 3 months ago
Address-Indexed Memory Disambiguation and Store-to-Load Forwarding
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
Sam S. Stone, Kevin M. Woley, Matthew I. Frank
IPPS
2000
IEEE
15 years 1 months ago
Predicting Performance on SMPs. A Case Study: The SGI Power Challenge
We study the issue of performance prediction on the SGIPower Challenge, a typical SMP. On such a platform, the cost of memory accesses depends on their locality and on contention ...
Nancy M. Amato, Jack Perdue, Mark M. Mathis, Andre...
95
Voted
IWMM
2010
Springer
118views Hardware» more  IWMM 2010»
15 years 2 months ago
Speculative parallelization using state separation and multiple value prediction
With the availability of chip multiprocessor (CMP) and simultaneous multithreading (SMT) machines, extracting thread level parallelism from a sequential program has become crucial...
Chen Tian, Min Feng, Rajiv Gupta
ICAS
2009
IEEE
139views Robotics» more  ICAS 2009»
15 years 4 months ago
Predicting Web Server Crashes: A Case Study in Comparing Prediction Algorithms
Abstract—Traditionally, performance has been the most important metrics when evaluating a system. However, in the last decades industry and academia have been paying increasing a...
Javier Alonso, Jordi Torres, Ricard Gavaldà
83
Voted
ICS
1999
Tsinghua U.
15 years 1 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...