1043 search results - page 11 / 209 » Reading, Writing and Relations |
HPCA
1997
IEEE
15 years 1 months ago
1997
IEEE
Processors with write-through caches typically require a write buffer to hide the write latency to the next level of memory hierarchy and to reduce write traffic. A write buffer ...
ASPLOS
1991
ACM
15 years 1 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
PRDC
1999
IEEE
15 years 2 months ago
1999
IEEE
The parity calculation technique of the RAID5 provides high reliability, efficient disk space usage, and good read performance for parallel-disk-array configurations. However, it ...
MSS
1999
IEEE
15 years 2 months ago
1999
IEEE
We propose a new method of ensuring the redundant storage of information on tertiary storage, especially tape storage. Conventional methods for redundant data storage on tape incl...
VLDB
1992
ACM
15 years 1 months ago
1992
ACM
