Sciweavers

470 search results - page 74 / 94
» Reading a Neural Code
Sort
View
CSREAESA
2009
15 years 27 days ago
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
Bradley F. Dutton, Charles E. Stroud
IEE
2008
120views more  IEE 2008»
14 years 12 months ago
Reducing the use of nullable types through non-null by default and monotonic non-null
With Java 5 annotations, we note a marked increase in tools that can statically detect potential null dereferences. To be effective such tools require that developers annotate decl...
Patrice Chalin, Perry R. James, Frédé...
ADHOC
2004
127views more  ADHOC 2004»
14 years 11 months ago
A distributed and adaptive signal processing approach to exploiting correlation in sensor networks
We propose a novel approach to reducing energy consumption in sensor networks using a distributed adaptive signal processing framework and efficient algorithm 1 . While the topic o...
Jim Chou, Dragan Petrovic, Kannan Ramchandran
VLSISP
2008
147views more  VLSISP 2008»
14 years 10 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
IPPS
2010
IEEE
14 years 9 months ago
Consistency in hindsight: A fully decentralized STM algorithm
Abstract--Software transactional memory (STM) algorithms often rely on centralized components to achieve atomicity, isolation and consistency. In a distributed setting, centralized...
Annette Bieniusa, Thomas Fuhrmann