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CODES
2005
IEEE
15 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
111
Voted
ANCS
2005
ACM
15 years 3 months ago
Segmented hash: an efficient hash table implementation for high performance networking subsystems
Hash tables provide efficient table implementations, achieving O(1), query, insert and delete operations at low loads. However, at moderate or high loads collisions are quite freq...
Sailesh Kumar, Patrick Crowley
79
Voted
TLCA
2005
Springer
15 years 3 months ago
Privacy in Data Mining Using Formal Methods
There is growing public concern about personal data collected by both private and public sectors. People have very little control over what kinds of data are stored and how such da...
Stan Matwin, Amy P. Felty, István T. Hern&a...
EWSA
2004
Springer
15 years 2 months ago
Generation and Enactment of Controllers for Business Architectures Using MDA
Model Driven Architecture (MDA) is an initiative of the OMG in which the software development process is driven by various software-related models describing the software to be gen...
Günter Graw, Peter Herrmann
MTDT
2003
IEEE
100views Hardware» more  MTDT 2003»
15 years 2 months ago
Optimal Spare Utilization in Repairable and Reliable Memory Cores
Advances in System-on-Chip (SoC) technology rely on manufacturing and assembling high-performance system cores for many critical applications. Among these cores, memory occupies t...
Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-...