1941 search results - page 178 / 389 » Reasoning about Computations Using Two-Levels of Logic |
108
Voted
AIPS
2010
15 years 6 months ago
2010
The utility of including loops in plans has been long recognized by the planning community. Loops in a plan help increase both its applicability and the compactness of representat...
117
click to vote
GLVLSI
2009
IEEE
15 years 10 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
128
Voted
SLP
1994
15 years 4 months ago
1994
We consider a hierarchy of modal event calculi to represent and reason about partially ordered events. These calculi are based on the model of time and change of Kowalski and Sergo...
117
click to vote
VMCAI
2009
Springer
15 years 10 months ago
2009
Springer
—A variety of partial modeling formalisms, aimed re and reason about abstractions, have been proposed. Some, e.g., Kripke Modal Transition Systems (KMTSs) put strong restrictions...
143
Voted
AINA
2003
IEEE
15 years 7 months ago
2003
IEEE
Condition Data Flow Diagrams (CDFDs) are a formalized notation resulting from the integration of Yourdon Data Flow Diagrams, Petri Nets, and pre-post notation. They are used in th...