Reasoning, problem solving, indeed the general process of acquiring knowledge, is not an isolated, homogenous affair involving a one agent using a single form of representation, b...
This paper presents a new approach to timing optimization for FPGA designs, namely incremental physical resynthesis, to answer the challenge of effectively integrating logic and p...
Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi...
Retargetable C compilers are nowadays widely used to quickly obtain compiler support for new embedded processors and to perform early processor architecture exploration. One frequ...
Manuel Hohenauer, Christoph Schumacher, Rainer Leu...
Abstract—The Reliable Server Pooling (RSerPool) architecture is the IETF’s new standard for a lightweight server redundancy and session failover framework to support availabili...
Xing Zhou, Thomas Dreibholz, Fu Fa, Wencai Du, Erw...
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...