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IPPS
1998
IEEE
15 years 2 months ago
PACE: Processor Architectures for Circuit Emulation
We describe a family of reconfigurable parallel architectures for logic emulation. They are supposed to be applicable like conventional FPGAs, while covering a larger range of circ...
Reiner Kolla, Oliver Springauf
GRID
2004
Springer
15 years 3 months ago
High Performance Threaded Data Streaming for Large Scale Simulations
We have developed a threaded parallel data streaming approach using Logistical Networking (LN) to transfer multi-terabyte simulation data from computers at NERSC to our local anal...
Viraj Bhat, Scott Klasky, Scott Atchley, Micah Bec...
MIDDLEWARE
2005
Springer
15 years 3 months ago
A reconfigurable group management middleware service for wireless sensor networks
Group management service plays a key role in wireless sensor networks (WSNs) as it provides support to high level middleware services such as object tracking, security, fault-tole...
Mardoqueu Vieira, Nelson Souto Rosa
ERSA
2009
149views Hardware» more  ERSA 2009»
14 years 7 months ago
Hardware-Optimized Ziggurat Algorithm for High-Speed Gaussian Random Number Generators
Many scientific and engineering applications, which are increasingly being ported from software to reconfigurable platforms, require Gaussian-distributed random numbers. Thus, the...
Hassan Edrees, Brian Cheung, McCullen Sandora, Dav...
DSOM
2007
Springer
15 years 4 months ago
AURIC: A Scalable and Highly Reusable SLA Compliance Auditing Framework
Abstract. Service Level Agreements (SLA) are needed to allow business interactions to rely on Internet services. Service Level Objectives (SLO) specify the committed performance le...
Hasan, Burkhard Stiller