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ISCAS
2006
IEEE
101views Hardware» more  ISCAS 2006»
15 years 4 months ago
A cost-effective reconfigurable accelerator for platform-based SOC design
In this paper, we propose a cost-effective reconfigurable accelerator for the platform-based system-on-a-chip (SoC) design. Based on the proposed design methodology, the reconfigu...
Lan-Da Van, Hsin-Fu Luo, Nien-Hsiang Chang, Chun-M...
ICPPW
2005
IEEE
15 years 3 months ago
Performance Evaluation of High-Speed Interconnects Using Dense Communication Patterns
We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these int...
Rod Fatoohi, Ken Kardys, Sumy Koshy, Soundarya Siv...
FCCM
2011
IEEE
251views VLSI» more  FCCM 2011»
14 years 1 months ago
A Scalable Multi-FPGA Platform for Complex Networking Applications
Abstract—Ballooning traffic volumes and increasing linkspeeds require ever high compute power to perform complex real-time processing of network packets. FPGAs have already been...
Sascha Mühlbach, Andreas Koch
DAC
2000
ACM
15 years 11 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...
DSD
2009
IEEE
145views Hardware» more  DSD 2009»
15 years 4 months ago
High Performance Image Processing on a Massively Parallel Processor Array
Multicore and manycore processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementati...
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bru...