Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...
The BaBar experiment at the Stanford Linear Accelerator Center (SLAC) is designed to perform a high precision investigation of the decays of the B-meson produced from electron-pos...
We present the WarpEngine, an architecture designed for realtime image-based rendering of natural scenes from arbitrary viewpoints. The modeling primitives are real-world images w...
Voicu Popescu, John G. Eyles, Anselmo Lastra, Josh...
The probability of failures in software distributed shared memory (SDSM) increases as the system size grows. This paper introduces a new, efficient message logging technique, call...
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...