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IEEEPACT
2008
IEEE
15 years 4 months ago
Multi-optimization power management for chip multiprocessors
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
Ke Meng, Russ Joseph, Robert P. Dick, Li Shang
ATAL
2007
Springer
15 years 4 months ago
Batch reinforcement learning in a complex domain
Temporal difference reinforcement learning algorithms are perfectly suited to autonomous agents because they learn directly from an agent’s experience based on sequential actio...
Shivaram Kalyanakrishnan, Peter Stone
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
15 years 4 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski
DATE
2006
IEEE
152views Hardware» more  DATE 2006»
15 years 3 months ago
Adaptive chip-package thermal analysis for synthesis and design
Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cooling. To address these challenges, thermal analy...
Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Li...
ISLPED
2003
ACM
122views Hardware» more  ISLPED 2003»
15 years 3 months ago
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Ever shrinking device sizes and innovative micro-architectural and circuit design techniques have made it possible to have multi-million transistor systems running at multi-gigahe...
Venkata Syam P. Rapaka, Diana Marculescu
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