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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
15 years 2 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
MOBIQUITOUS
2005
IEEE
15 years 3 months ago
MAIPAN - Middleware for Application Interconnection in Personal Area Networks
This paper proposes the Middleware for Application Interconnection in Personal Area Networks (MAIPAN), a middleware that provides a uniform computing environment for creating dyna...
Miklós Aurél Rónai, Kristof F...
ASPDAC
2005
ACM
142views Hardware» more  ASPDAC 2005»
15 years 2 days ago
An AMBA AHB-based reconfigurable SOC architecture using multiplicity of dedicated flyby DMA blocks
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
Adeoye Olugbon, Sami Khawam, Tughrul Arslan, Ioann...
BTW
1999
Springer
145views Database» more  BTW 1999»
15 years 2 months ago
A Multi-Tier Architecture for High-Performance Data Mining
Data mining has been recognised as an essential element of decision support, which has increasingly become a focus of the database industry. Like all computationally expensive data...
Ralf Rantzau, Holger Schwarz
IPPS
2000
IEEE
15 years 2 months ago
Reconfigurable Parallel Sorting and Load Balancing on a Beowulf Cluster: HeteroSort
HeteroSort load balances and sorts within static or dynamic networks using a conceptual torus mesh. We ported HeteroSort to a 16-node Beowulf cluster with a central switch architec...
Pamela Yang, Timothy M. Kunau, Bonnie Holte Bennet...