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ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 7 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for applicationāˆ’specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
CORR
2010
Springer
198views Education» more  CORR 2010»
15 years 3 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka
EWSN
2009
Springer
16 years 3 months ago
QoS Management for Wireless Sensor Networks with a Mobile Sink
The problem of configuration of Wireless Sensor Networks is an interesting challenge. The objective is to find the settings, for each sensor node, that optimise certain task-level ...
Rob Hoes, Twan Basten, Wai-Leong Yeow, Chen-Khong ...
DAC
2009
ACM
16 years 4 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
ICS
1999
Tsinghua U.
15 years 7 months ago
Realizing the performance potential of the virtual interface architecture
The Virtual Interface (VI) Architecture provides protected userlevel communication with high delivered bandwidth and low permessage latency, particularly for small messages. The V...
Evan Speight, Hazim Abdel-Shafi, John K. Bennett