Sciweavers

6666 search results - page 254 / 1334
» Reconfigurable Computing for High Performance Networking App...
Sort
View
VLSID
2004
IEEE
209views VLSI» more  VLSID 2004»
16 years 3 months ago
An Architecture for Motion Estimation in the Transform Domain
demanding algorithm of a video encoder. It is known that about 60% ~ 80% of the total computation time is consumed for motion estimation [1]. The second is its high impact on the v...
J. Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, ...
HPCA
2009
IEEE
16 years 4 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
DSRT
2009
IEEE
15 years 7 months ago
Switching to High Gear: Opportunities for Grand-Scale Real-Time Parallel Simulations
The recent emergence of dramatically large computational power, spanning desktops with multicore processors and multiple graphics cards to supercomputers with 105 processor cores,...
Kalyan S. Perumalla
CASES
2005
ACM
15 years 5 months ago
Software-directed power-aware interconnection networks
Interconnection networks have been deployed as the communication fabric in a wide range of parallel computer systems. With recent technological trends allowing growing quantities ...
Vassos Soteriou, Noel Eisley, Li-Shiuan Peh
117
Voted
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
15 years 9 months ago
Tradeoffs in designing accelerator architectures for visual computing
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
Aqeel Mahesri, Daniel R. Johnson, Neal C. Crago, S...