26 search results - page 3 / 6 » Reconfigurable Hardware Implementations of Tweakable Enciphe... |
FPGA
2010
ACM
13 years 6 months ago
2010
ACM
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
ARC
2006
Springer
13 years 10 months ago
2006
Springer
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
MAM
2006
13 years 6 months ago
2006
FPGA placement and routing is time consuming, often serving as the major obstacle inhibiting a fast edit-compile-test loop in prototyping and development and the major obstacle pr...
CF
2006
ACM
14 years 9 days ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...