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» Reconfigurable Hardware for Power-over-Fiber Applications
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DATE
2002
IEEE
118views Hardware» more  DATE 2002»
15 years 2 months ago
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
Marcos Sanchez-Elez, Milagros Fernández, Ra...
ASAP
2007
IEEE
130views Hardware» more  ASAP 2007»
15 years 1 months ago
A Self-Reconfigurable Implementation of the JPEG Encoder
Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a ...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
15 years 3 months ago
An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
Michalis D. Galanis, Gregory Dimitroulakos, Consta...
ASAP
2009
IEEE
79views Hardware» more  ASAP 2009»
15 years 1 months ago
Reconfigurable SWP Operator for Multimedia Processing
Shafqat Khan, Emmanuel Casseau, Daniel Menard
EUROGP
2008
Springer
128views Optimization» more  EUROGP 2008»
14 years 11 months ago
Hardware Accelerators for Cartesian Genetic Programming
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidat...
Zdenek Vasícek, Lukás Sekanina