444 search results - page 45 / 89 » Reconfigurable Hardware for Power-over-Fiber Applications |
FPL
2004
Springer
15 years 3 months ago
2004
Springer
When designing SoCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion o...
FPL
2007
Springer
15 years 4 months ago
2007
Springer
In this paper, we present the DWARV C-to-VHDL generation toolset. The toolset provides support for broad range of application domains. It exploits the operation parallelism, avail...
FCCM
2004
IEEE
15 years 1 months ago
2004
IEEE
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
ASAP
2005
IEEE
15 years 3 months ago
2005
IEEE
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
VLSISP
2008
14 years 10 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...