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CODES
2008
IEEE
15 years 4 months ago
Dynamic tuning of configurable architectures: the AWW online algorithm
Architectures with software-writable parameters, or configurable architectures, enable runtime reconfiguration of computing platforms to the applications they execute. Such dynami...
Chen Huang, David Sheldon, Frank Vahid
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
15 years 1 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
GECCO
2003
Springer
120views Optimization» more  GECCO 2003»
15 years 3 months ago
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation
Abstract. Multi-FPGA systems (MFS) are used for a great variety of applications, for instance, dynamically re-configurable hardware applications, digital circuit emulation, and num...
José Ignacio Hidalgo, Francisco Ferná...
ERSA
2009
109views Hardware» more  ERSA 2009»
14 years 7 months ago
An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors
An increasing number of embedded system solutions in space, military, and consumer electronics applications rely on processor cores inside reconfigurable logic devices. Ensuring da...
Austin Rogers, Aleksandar Milenkovic
ERSA
2010
153views Hardware» more  ERSA 2010»
14 years 7 months ago
VAPRES: A Customizable and Flexible Base Architecture for Partially Reconfigurable Systems
- Partial reconfiguration (PR) enhances traditional FPGA-based high-performance reconfigurable computing by providing additional benefits such as reduced area and memory requiremen...
Ann Gordon-Ross, Abelardo Jara-Berrocal