444 search results - page 58 / 89 » Reconfigurable Hardware for Power-over-Fiber Applications |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
CODES
2002
IEEE
15 years 2 months ago
2002
IEEE
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
ASPDAC
2005
ACM
14 years 12 months ago
2005
ACM
– We propose a System-on-Chip (SoC) architecture for reconfigurable applications based on the AMBA HighSpeed Bus (AHB). The architecture features multiple low-area flyby DMA bloc...
FPL
2008
Springer
14 years 11 months ago
2008
Springer
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
104
click to vote
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
This paper presents ReMAP, a reconfigurable architecture geared towards accelerating and parallelizing applications within a heterogeneous CMP. In ReMAP, threads share a common rec...