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ERSA
2006
186views Hardware» more  ERSA 2006»
14 years 11 months ago
The Case for High Level Programming Models for Reconfigurable Computers
In this paper we first outline and discuss the issues of currently accepted computational models for hybrid CPU/FPGA systems. Then, we discuss the need for researchers to develop ...
David L. Andrews, Ron Sass, Erik Anderson, Jason A...
FPL
2009
Springer
145views Hardware» more  FPL 2009»
15 years 2 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
15 years 2 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...
DSD
2010
IEEE
121views Hardware» more  DSD 2010»
14 years 8 months ago
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA
Orthogonal Frequency Division Multiplexing (OFDM) can provide a flexible usage of the spectrum by controlling individual subcarriers. Sets of subcarriers can be zero-modulated to a...
Adolfo Recio, Peter M. Athanas
ICRA
2007
IEEE
160views Robotics» more  ICRA 2007»
15 years 4 months ago
Morphing Bus: A rapid deployment computing architecture for high performance, resource-constrained robots
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...
Colin D'Souza, Byung Hwa Kim, Richard M. Voyles