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» Reconfigurations in Graphs and Grids
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TC
1998
14 years 11 months ago
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
—The very high levels of integration and submicron device sizes used in current and emerging VLSI technologies for FPGAs lead to higher occurrences of defects and operational fau...
Fran Hanchek, Shantanu Dutt
JDA
2007
62views more  JDA 2007»
14 years 11 months ago
Maximum integer multiflow and minimum multicut problems in two-sided uniform grid graphs
In this paper, we deal with the maximum integer multiflow and the minimum multicut problems in rectilinear grid graphs with uniform capacities on the edges. The first problem is...
Cédric Bentz, Marie-Christine Costa, Fr&eac...
85
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EURODAC
1994
IEEE
105views VHDL» more  EURODAC 1994»
15 years 4 months ago
On Design Rule Correct Maze Routing
This paper addresses the problem of design rule correct routing, i.e. the avoidance of illegal wiring patterns during routing. These illegal wiring patterns are due to the set of ...
Ed P. Huijbregts, Jos T. J. van Eijndhoven, Jochen...
JGAA
1998
116views more  JGAA 1998»
14 years 11 months ago
New Lower Bounds For Orthogonal Drawings
An orthogonal drawing of a graph is an embedding of the graph in the two-dimensional grid such that edges are routed along grid-lines. In this paper we explore lower bounds for or...
Therese C. Biedl