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128
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ICCAD
1994
IEEE
76views Hardware» more  ICCAD 1994»
15 years 4 months ago
An efficient procedure for the synthesis of fast self-testable controller structures
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
Sybille Hellebrand, Hans-Joachim Wunderlich
ICS
1993
Tsinghua U.
15 years 4 months ago
The NuMesh: A Modular, Scalable Communications Substrate
Many standardized hardware communication interfaces offer runtime flexibility and configurability at the cost of efficiency. An alternate approach is the use of a highly-effic...
Steve Ward, Karim Abdalla, Rajeev Dujari, Michael ...
CODES
2009
IEEE
15 years 4 months ago
Cycle count accurate memory modeling in system level design
In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accu...
Yi-Len Lo, Mao Lin Li, Ren-Song Tsay
90
Voted
DEBS
2010
ACM
15 years 4 months ago
Predictive publish/subscribe matching
A new publish/subscribe capability is presented: the ability to predict the likelihood that a subscription will be matched at some point in the future. Composite subscriptions con...
Vinod Muthusamy, Haifeng Liu, Hans-Arno Jacobsen
112
Voted
GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...