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VTS
2002
IEEE
108views Hardware» more  VTS 2002»
15 years 11 months ago
On Using Efficient Test Sequences for BIST
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
René David, Patrick Girard, Christian Landr...
ICCAD
2002
IEEE
89views Hardware» more  ICCAD 2002»
15 years 11 months ago
Free space management for cut-based placement
IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-dow...
Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
159
Voted
VMV
2001
115views Visualization» more  VMV 2001»
15 years 7 months ago
Segmentation-Based Postprocessing in Real-Time Immersive Video Conferencing
We present a novel, real-time disparity analysis frame work developed for immersive teleconferencing. This two-stage method computes a limited number of highly reliable disparitie...
Oliver Schreer, Serap Askar, Nicole Brandenburg, P...
VTS
1996
IEEE
126views Hardware» more  VTS 1996»
15 years 10 months ago
Automatic test generation using genetically-engineered distinguishing sequences
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
ICCAD
2001
IEEE
101views Hardware» more  ICCAD 2001»
16 years 3 months ago
Instruction Generation for Hybrid Reconfigurable Systems
In this work, we present an algorithm for simultaneous template generation and matching. The algorithm profiles the graph and iteratively contracts edges to create the templates. ...
Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzad...