High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
IP blocks and large macro cells are increasingly prevalent in physical design, actually causing an increase in the available free space for the dust logic. We observe that top-dow...
We present a novel, real-time disparity analysis frame work developed for immersive teleconferencing. This two-stage method computes a limited number of highly reliable disparitie...
Oliver Schreer, Serap Askar, Nicole Brandenburg, P...
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
In this work, we present an algorithm for simultaneous template generation and matching. The algorithm profiles the graph and iteratively contracts edges to create the templates. ...
Ryan Kastner, Seda Ogrenci Memik, Elaheh Bozorgzad...