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117
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IPPS
1998
IEEE
15 years 4 months ago
Memory Hierarchy Management for Iterative Graph Structures
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
Ibraheem Al-Furaih, Sanjay Ranka
109
Voted
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 4 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
ICSE
1997
IEEE-ACM
15 years 4 months ago
Characterizing and Modeling the Cost of Rework in a Library of Reusable Software Components
1 In this paper we characterize and model the cost of rework in a Component Factory (CF) organization. A CF is responsible for developing and packaging reusable software components...
Victor R. Basili, Steven E. Condon, Khaled El Emam...
SIGMETRICS
1994
ACM
113views Hardware» more  SIGMETRICS 1994»
15 years 4 months ago
Shade: A Fast Instruction-Set Simulator for Execution Profiling
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...
Robert F. Cmelik, David Keppel
129
Voted
CCGRID
2009
IEEE
15 years 4 months ago
Hierarchical Caches for Grid Workflows
From personal software to advanced systems, caching mechanisms have steadfastly been a ubiquitous means for reducing workloads. It is no surprise, then, that under the grid and clu...
David Chiu, Gagan Agrawal