31 search results - page 1 / 7 » Reduced Latency IEEE Floating-Point Standard Adder Architect... |
ARITH
1999
IEEE
15 years 2 months ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
101
Voted
TC
2010
14 years 8 months ago
2010
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
85
Voted
ARITH
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
ARITH
1997
IEEE
15 years 2 months ago
1997
IEEE
Engineering design methodology recommends designing a system as follows: Start with an unambiguous speci cation, partition the system into blocks, specify the functionality of eac...
ARITH
2007
IEEE
15 years 4 months ago
2007
IEEE
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...