24 search results - page 2 / 5 » Reduced Precision Checking for a Floating Point Adder |
ARITH
1999
IEEE
15 years 1 months ago
1999
IEEE
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
TC
2010
14 years 8 months ago
2010
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
ARITH
1997
IEEE
15 years 1 months ago
1997
IEEE
Engineering design methodology recommends designing a system as follows: Start with an unambiguous speci cation, partition the system into blocks, specify the functionality of eac...
CAL
2007
14 years 9 months ago
2007
Abstract—Some processors designed for consumer applications, such as Graphics Processing Units (GPUs) and the CELL processor, promise outstanding floating-point performance for ...
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CADE
2010
Springer
14 years 10 months ago
2010
Springer
Abstract. In the context of deductive program verification, supporting floatingpoint computations is tricky. We propose an expressive language to formally specify behavioral proper...