24 search results - page 3 / 5 » Reduced Precision Checking for a Floating Point Adder |
FPL
2007
Springer
15 years 3 months ago
2007
Springer
In this paper we present Minibit+, an approach that optimizes the bit-widths of fixed-point and floating-point designs, while guaranteeing accuracy. Our approach adopts differen...
ARITH
2009
IEEE
15 years 4 months ago
2009
IEEE
The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand v...
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DSD
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper we present an analysis of the minimal hardware precision required to implement Support Vector Machine (SVM) classification within a Logarithmic Number System archite...
IFIP
1998
Springer
15 years 1 months ago
1998
Springer
A conservative implementation of a predicate returns true only if the exact predicate is true. That is, we accept a one sided error for the implementation. For geometric predicate...
ERSA
2007
14 years 11 months ago
2007
The emergence of high-density reconfigurable hardware devices gives scientists and engineers an option to accelerating their numerical computing applications on low-cost but power...