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» Reduced Precision Checking for a Floating Point Adder
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TC
2008
14 years 9 months ago
High-Performance Mixed-Precision Linear Solver for FPGAs
Compared to higher-precision data formats, lower-precision data formats result in higher performance for computationally intensive applications on FPGAs because of their lower res...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
14 years 11 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
SCAM
2008
IEEE
15 years 4 months ago
Automated Detection of Code Vulnerabilities Based on Program Analysis and Model Checking
Ensuring the correctness and reliability of software systems is one of the main problems in software development. Model checking, a static analysis method, is preponderant in impr...
Lei Wang, Qiang Zhang, PengChao Zhao
ISSAC
2009
Springer
144views Mathematics» more  ISSAC 2009»
15 years 4 months ago
H-LLL: using householder inside LLL
We describe a new LLL-type algorithm, H-LLL, that relies on Householder transformations to approximate the underlying Gram-Schmidt orthogonalizations. The latter computations are ...
Ivan Morel, Damien Stehlé, Gilles Villard
58
Voted
ICRA
2009
IEEE
113views Robotics» more  ICRA 2009»
14 years 7 months ago
Study on adhesion force reduction and state estimation by piezo-transducer
Our previous paper presented a method for reducing adhesion forces by oscillation and showed the adhesion state can be checked by analyzing the data obtained by laser displacement ...
Tetsuyou Watanabe, Makoto Iwasaki, Hidekazu Matsum...