64 search results - page 5 / 13 » Reducing Boarding Time: Synthesis of Improved Genetic Algori... |
106
Voted
PDPTA
2000
15 years 1 months ago
2000
Exploiting compile time knowledge to improve memory bandwidth can produce noticeable improvements at run-time [13, 1]. Allocating the data structure [13] to separate memories when...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
Conventional high-level synthesis uses the worst case delay to relate all inputs to all outputs of an operation. This is a very conservative approximation of reality, especially i...
90
Voted
VTS
2007
IEEE
15 years 6 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
83
Voted
DAC
2004
ACM
16 years 19 days ago
2004
ACM
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
102
click to vote
ATS
2000
IEEE
15 years 4 months ago
2000
IEEE
Testing of embedded cores is very difficult in SOC (system-on-a-chip), since the core user may not know the gate level implementation of the core, and the controllability and obse...