60 search results - page 12 / 12 » Reducing DRAM Latencies with an Integrated Memory Hierarchy ... |
HPCA
1998
IEEE
13 years 10 months ago
1998
IEEE
The frequency of accesses to remote data is a key factor affecting the performance of all Distributed Shared Memory (DSM) systems. Remote data caching is one of the most effective...
IEEEPACT
2008
IEEE
14 years 20 days ago
2008
IEEE
Moore’s Law and the drive towards performance efficiency have led to the on-chip integration of general-purpose cores with special-purpose accelerators. Pangaea is a heterogeneo...
SC
2009
ACM
14 years 1 months ago
2009
ACM
Reconfigurable computing (RC) systems based on FPGAs are becoming an increasingly attractive solution to building parallel systems of the future. Applications targeting such syste...
PPOPP
2011
ACM
12 years 9 months ago
2011
ACM
In recent years, GPUs have emerged as an extremely cost-effective means for achieving high performance. Many application developers, including those with no prior parallel program...
SIGARCH
2008
13 years 6 months ago
2008
As CMP platforms are widely adopted, more and more cores are integrated on to the die. To reduce the off-chip memory access, the last level cache is usually organized as a distribu...