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133
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ACMMSP
2006
ACM
250views Hardware» more  ACMMSP 2006»
15 years 5 months ago
What do high-level memory models mean for transactions?
Many people have proposed adding transactions, or atomic blocks, to type-safe high-level programming languages. However, researchers have not considered the semantics of transacti...
Dan Grossman, Jeremy Manson, William Pugh
ISCA
2007
IEEE
143views Hardware» more  ISCA 2007»
15 years 6 months ago
Performance pathologies in hardware transactional memory
Hardware Transactional Memory (HTM) systems reflect choices from three key design dimensions: conflict detection, version management, and conflict resolution. Previously propos...
Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Y...
97
Voted
PLDI
2006
ACM
15 years 5 months ago
Optimizing memory transactions
Atomic blocks allow programmers to delimit sections of code as ‘atomic’, leaving the language’s implementation to enforce atomicity. Existing work has shown how to implement...
Timothy L. Harris, Mark Plesko, Avraham Shinnar, D...
86
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VLSID
2008
IEEE
128views VLSI» more  VLSID 2008»
16 years 1 days ago
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
Banit Agrawal, Timothy Sherwood, Chulho Shin, Simo...
HPCA
2005
IEEE
16 years 17 hour ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob