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» Reducing Parallel Overheads Through Dynamic Serialization
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IEEEPACT
2005
IEEE
15 years 3 months ago
A Distributed Control Path Architecture for VLIW Processors
VLIW architectures are popular in embedded systems because they offer high-performance processing at low cost and energy. The major problem with traditional VLIW designs is that t...
Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael...
HPCA
2008
IEEE
15 years 10 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
CODES
2011
IEEE
13 years 9 months ago
DistRM: distributed resource management for on-chip many-core systems
The trend towards many-core systems comes with various issues, among them their highly dynamic and non-predictable workloads. Hence, new paradigms for managing resources of many-c...
Sebastian Kobbe, Lars Bauer, Daniel Lohmann, Wolfg...
DAWAK
2010
Springer
14 years 10 months ago
Experience in Extending Query Engine for Continuous Analytics
: Experience in Extending Query Engine for Continuous Analytics Qiming Chen, Meichun Hsu HP Laboratories HPL-2010-44 In-Database Stream Processing Combining data warehousing and s...
Qiming Chen, Meichun Hsu
TVLSI
2010
14 years 4 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...