135 search results - page 1 / 27 » Reducing Power Dissipation in SRAM during Test |
JOLPE
2006
13 years 6 months ago
2006
MTV
2007
IEEE
14 years 16 days ago
2007
IEEE
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
DATE
2006
IEEE
14 years 10 days ago
2006
IEEE
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
DAC
1997
ACM
13 years 10 months ago
1997
ACM
An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of l...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...