135 search results - page 20 / 27 » Reducing Power Dissipation in SRAM during Test |
ICCAD
2005
IEEE
15 years 6 months ago
2005
IEEE
: Double-Gate (DG) transistors have emerged as promising devices for nano-scale circuits due to their better scalability compared to bulk CMOS. Among the various types of DG device...
TVLSI
2002
14 years 9 months ago
2002
Gate diffusion input (GDI)--a new technique of low-power digital combinatorial circuit design--is described. This technique allows reducing power consumption, propagation delay, an...
MTDT
2003
IEEE
15 years 2 months ago
2003
IEEE
Memory cores (especially SRAM cores) used on a system chip usually come from a memory compiler. Commercial memory compilers have their limitation— a large memory may need to be ...
113
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ATS
2005
IEEE
15 years 3 months ago
2005
IEEE
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
122
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DFT
2005
IEEE
14 years 11 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...