287 search results - page 10 / 58 » Reducing Power in High-Performance Microprocessors |
104
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ISCA
2009
IEEE
15 years 6 months ago
2009
IEEE
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
130
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ICCAD
2010
IEEE
14 years 9 months ago
2010
IEEE
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
USENIX
2004
15 years 1 months ago
2004
OKWS is a toolkit for building fast and secure Web services. It provides Web developers with a small set of tools that has proved powerful enough to build complex systems with lim...
ARITH
2003
IEEE
15 years 5 months ago
2003
IEEE
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
With technology advances, the number of cores integrated on a chip and their speed of operation is increasing. This, in turn is leading to a significant increase in chip temperat...