287 search results - page 11 / 58 » Reducing Power in High-Performance Microprocessors |
IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we inv...
CODES
2006
IEEE
15 years 3 months ago
2006
IEEE
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
CONCURRENCY
2010
14 years 9 months ago
2010
Over the past decade the number of processors in the high performance facilities went up to hundreds of thousands. As a direct consequence, while the computational power follow th...
83
Voted
ICCD
2008
IEEE
15 years 6 months ago
2008
IEEE
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines(T-lin...
78
Voted
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
— To address the performance limitation brought by the scaling issues of on-chip global wires, a new configuration for global wiring using on-chip lossy transmission lines is pr...